MT46V32M4TG-6T:D TR

128Mb: x4, x8, x16 DDR SDRAM Features Double Data Rate (DDR) SDRAM MT46V32M4 – 8 Meg x 4 x 4 banks MT46V16M8 – 4 Meg x 8 x 4 banks MT46V8M16 – 2 Meg x 16 x 4 banks For the latest data sheet revisions, please refer to the Micron® Web site: www.micron.com/ddr2 Features Options • VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V • VDD = +2.6V ±0.1V, VDDQ = +2.6V ±0.1V (DDR 400) • Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two – one per byte) • Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle • Differential clock inputs (CK and CK#) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask (DM) for masking write data (x16 has two – one per byte) • Programmable burst lengths: 2, 4, or 8 • Auto Refresh and Self Refresh Modes • Longer lead TSOP for improved reliability (OCPL) • 2.5V I/O (SSTL_2 compatible) • Concurrent auto precharge option is supported • tRAS lockout supported (tRAP = tRCD) • Configuration 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 banks) • Plastic Package – OCPL 66-pin TSOP 66-pin TSOP (lead-free)1 • Timing – Cycle Time 5ns @ CL = 3 (DDR400) 6ns @ CL = 2.5 (DDR333)2 7.5ns @ CL = 2 (DDR266) 7.5ns @ CL = 2 (DDR266A) 7.5ns @ CL = 2.5 (DDR266B) • Self Refresh Standard Low Power Self Refresh • Temperature Rating Commercial (0°C to +70°C) Industrial (-40°C to +85°C) • Revision Marking 32M4 16M8 8M16 TG P -5B -6T -75E -75Z -75 None L None IT :A Notes: 1. Contact Micron for availability of lead-free products. 2. Not available in x16 configuration. Table 1: Configuration Addressing 32 Meg x 4 8 Meg x 4 x 4 banks 4K 4K (A0–A11) 4(BA0,BA1) 2K(A0–A9,A11) Configuration Refresh Count Row Addressing Bank Addressing Column Addressing Table 2: 16 Meg x 8 4 Meg x 8 x 4 banks 4K 4K (A0–A11) 4(BA0,BA1) 1K(A0–A9) 8 Meg x 16 2 Meg x 16 x 4 banks 4K 4K (A0–A11) 4(BA0,BA1) 512(A0–A8) Key Timing Parameters CL = CAS (READ) latency; minimum clock rate @ CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and CL = 3 (-5B). Clock Rate Speed Grade -5B -6 6T -75E/75Z -75 CL = 2 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 09005aef8074a655 128MBDDRx4x8x16_1.fm - Rev. J 4/05 EN CL = 2.5 167 MHz 167 MHz 167 MHz 133 MHz 133 MHz CL = 3 200 MHz N/A N/A N/A N/A 1 Data-Out Window 1.6ns 2.1ns 2.0ns 2.5ns 2.5ns Access Window ±0.70ns ±0.70ns ±0.70ns ±0.75ns ±0.75ns DQS–DQ Skew +0.40ns +0.40ns +0.45ns +0.50ns +0.50ns Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.